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| LTC2492 24-Bit 2-/4-Channel ADC with Easy Drive Input Current Cancellation FEATURES DESCRIPTION The LTC(R)2492 is a 4-channel (2-channel differential), 24-bit, No Latency TM ADC with Easy DriveTM technology. The patented sampling scheme eliminates dynamic input current errors and the shortcomings of on-chip buffering through automatic cancellation of differential input current. This allows large external source impedances and rail-torail input signals to be directly digitized while maintaining exceptional DC accuracy. The LTC2492 includes a high accuracy temperature sensor and an integrated oscillator. This device can be configured to measure an external signal (from combinations of 4 analog input channels operating in single-ended or differential modes) or its internal temperature sensor. It can be programmed to reject line frequencies of 50Hz, 60Hz, or simultaneous 50Hz/60Hz and configured to double its output rate. The integrated temperature sensor offers 1/30th C resolution and 2C absolute accuracy. The LTC2492 allows a wide common mode input range (0V to VCC), independent of the reference voltage. Any combination of single-ended or differential inputs can be selected and the first conversion after a new channel selection is valid. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. No Latency and Easy Drive are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Up to 2 Differential or 4 Single-Ended Inputs Easy Drive Technology Enables Rail-to-Rail Inputs with Zero Differential Input Current Directly Digitizes High Impedance Sensors with Full Accuracy 600nV RMS Noise Integrated High Accuracy Temperature Sensor GND to VCC Input/Reference Common Mode Range Programmable 50Hz, 60Hz, or Simultaneous 50Hz/60Hz Rejection Mode 2ppm INL, No Missing Codes 1ppm Offset and 15ppm Full-Scale Error 2x Speed Mode/Reduced Power Mode (15Hz Using Internal Oscillator and 80A at 7.5Hz Output) No Latency: Digital Filter Settles in a Single Cycle, Even After a New Channel is Selected Single Supply 2.7V to 5.5V Operation (0.8mW) Internal Oscillator Tiny DFN 4mm x 3mm Package APPLICATIONS Direct Sensor Digitizer Direct Temperature Measurement Instrumentation Industrial Process Control TYPICAL APPLICATION Data Acquisition System with Temperature Compensation 2.7V TO 5.5V 10F 0.1F ABSOLUTE ERROR (C) 5 4 CH0 CH1 REF+ 24-BIT ADC WITH EASY-DRIVE IN- REF - SDI SCK SDO CS 4-WIRE SPI INTERFACE VCC 3 2 1 0 -1 -2 -3 -4 TEMPERATURE SENSOR FO OSC 2492 TA01a Absolute Temperature Error 4-CHANNEL MUX CH2 CH3 COM IN+ -5 -55 -30 -5 20 45 70 TEMPERATURE (C) 95 120 2492 TA01b 2492fb 1 LTC2492 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION FO SDI SCK CS SDO GND COM 1 2 3 4 5 6 7 15 14 REF - 13 REF + 12 VCC 11 CH3 10 CH2 9 CH1 8 CH0 Supply Voltage (VCC) ...................................- 0.3V to 6V Analog Input Voltage (CH0 to CH3, COM) ................. - 0.3V to (VCC + 0.3V) REF +, REF - .................................. - 0.3V to (VCC + 0.3V) Digital Input Voltage..................... - 0.3V to (VCC + 0.3V) Digital Output Voltage .................. - 0.3V to (VCC + 0.3V) Operating Temperature Range LTC2492C ................................................ 0C to 70C LTC2492I..............................................- 40C to 85C Storage Temperature Range...................- 65C to 150C DE PACKAGE 14-LEAD (4mm 3mm) PLASTIC DFN TJMAX = 125C, JA = 37C/W EXPOSED PAD (PIN 15) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH LTC2492CDE#PBF LTC2492IDE#PBF TAPE AND REEL LTC2492CDE#TRPBF LTC2492IDE#TRPBF PART MARKING* 2492 2492 PACKAGE DESCRIPTION 14-Lead (4mm x 3mm) Plastic DFN 14-Lead (4mm x 3mm) Plastic DFN TEMPERATURE RANGE 0C to 70C -40C to 85C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 3, 4) PARAMETER Resolution (No Missing Codes) Integral Nonlinearity Offset Error Offset Error Drift Positive Full-Scale Error Positive Full-Scale Error Drift Negative Full-Scale Error Negative Full-Scale Error Drift Total Unadjusted Error CONDITIONS 0.1V VREF VCC , -FS VIN +FS (Note 5) 5V VCC 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6) 2.7V VCC 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6) 2.5V VREF VCC , GND IN+ = IN- VCC (Note 14) 2.5V VREF VCC , GND IN+ = IN- V CC ELECTRICAL CHARACTERISTICS (NORMAL SPEED) MIN 24 TYP 2 1 0.5 10 MAX 10 2.5 25 UNITS Bits ppm of VREF ppm of VREF V nV/C ppm of VREF ppm of VREF/C ppm of VREF ppm of VREF/C ppm of VREF ppm of VREF ppm of VREF VRMS 2.5V VREF VCC , IN+ = 0.75VREF, IN- = 0.25VREF 2.5V VREF VCC , IN+ = 0.75VREF, IN- = 0.25VREF 2.5V VREF VCC , IN+ = 0.25VREF, IN- = 0.75VREF 2.5V VREF VCC , IN+ = 0.25VREF, IN- = 0.75VREF 5V VCC 5.5V, VREF = 2.5V, VIN(CM) = 1.25V 5V VCC 5.5V, VREF = 5V, VIN(CM) = 2.5V 2.7V VCC 5.5V, VREF = 2.5V, VIN(CM) = 1.25V 5.5V < VCC < 2.7V, 2.5V VREF VCC , GND IN + = IN - VCC (Note 13) TA = 27C (Note 14) 0.1 25 0.1 15 15 15 0.6 27.8 28.0 93.5 28.2 Output Noise Internal PTAT Signal Internal PTAT Temperature Coefficient mV V/C 2492fb 2 LTC2492 ELECTRICAL CHARACTERISTICS (2X SPEED) PARAMETER Resolution (No Missing Codes) Integral Nonlinearity Offset Error Offset Error Drift Positive Full-Scale Error Positive Full-Scale Error Drift Negative Full-Scale Error Negative Full-Scale Error Drift Output Noise CONDITIONS 0.1V VREF VCC , -FS VIN +FS (Note 5) 5V VCC 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6) 2.7V VCC 5.5V, VREF = 2.5V, VIN(CM) = 1.2V (Note 6) 2.5V VREF VCC , GND IN+ = IN - VCC (Note 14) 2.5V VREF VCC , GND IN+ = IN - VCC 2.5V VREF VCC , IN+ = 0.75VREF, IN - = 0.25VREF 2.5V VREF VCC , IN+ = 0.75VREF, IN - = 0.25VREF 2.5V VREF VCC , IN+ = 0.25VREF, IN - = 0.75VREF 2.5V VREF VCC , IN+ = 0.25VREF, IN - = 0.75VREF 5V VCC 2.5V, VREF = 5V, GND IN + = IN - VCC The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 3, 4) MIN 24 2 1 0.2 100 25 0.1 25 0.1 0.85 10 2 TYP MAX UNITS Bits ppm of VREF ppm of VREF mV nV/C ppm of VREF ppm of VREF/C ppm of VREF ppm of VREF/C VRMS CONVERTER CHARACTERISTICS PARAMETER Input Common Mode Rejection DC Input Common Mode Rejection 50Hz 2% Input Common Mode Rejection 60Hz 2% Input Normal Mode Rejection 50Hz 2% Input Normal Mode Rejection 60Hz 2% Input Normal Mode Rejection 50Hz/60Hz 2% Reference Common Mode Rejection DC Power Supply Rejection DC Power Supply Rejection, 50Hz 2% Power Supply Rejection, 60Hz 2% CONDITIONS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3) MIN TYP MAX UNITS dB dB dB 2.5V VREF VCC , GND IN+ = IN - VCC (Note 5) 2.5V VREF VCC 2.5V VREF VCC 2.5V VREF VCC VREF , GND IN+ = IN - V , GND IN+ = IN - V , GND IN+ = IN - V CC (Note 5) CC (Notes 5, 7) CC (Notes 5, 9) 140 140 140 110 110 87 120 140 120 120 120 120 120 2.5V VREF VCC , GND IN+ = IN - VCC (Note 5) 2.5V VREF VCC , GND IN+ = IN - VCC (Notes 5, 8) 2.5V VREF VCC , GND IN+ = IN - VCC (Note 5) = 2.5V, IN+ = IN - = GND VREF = 2.5V, IN+ = IN - = GND (Notes 7, 9) VREF = 2.5V, IN+ = IN - = GND (Notes 8, 9) dB dB dB dB dB dB dB 2492fb 3 LTC2492 ANALOG INPUT AND REFERENCE SYMBOL IN + IN - VIN FS LSB REF + REF - VREF CS(IN+) CS(IN -) CS(VREF) IDC_LEAK(IN+) IDC_LEAK(IN-) IDC_LEAK(REF+) IDC_LEAK(REF-) tOPEN QIRR PARAMETER Absolute/Common Mode IN + Voltage (IN+ Corresponds to the Selected Positive Input Channel) Absolute/Common Mode IN - Voltage (IN- Corresponds to the Selected Negative Input Channel) Input Differential Voltage Range (IN + - IN -) Full Scale of the Differential Input (IN + - IN -) Least Significant Bit of the Output Code Absolute/Common Mode REF+ Voltage Absolute/Common Mode REF - Voltage Reference Voltage Range (REF + - REF -) IN + Sampling Capacitance IN - Sampling Capacitance VREF Sampling Capacitance IN + DC Leakage Current IN - DC Leakage Current REF + DC Leakage Current REF - DC Leakage Current MUX Break-Before-Make MUX Off Isolation VIN = 2VP-P DC to 1.8MHz Sleep Mode, IN + = GND Sleep Mode, IN - = GND Sleep Mode, REF + = VCC Sleep Mode, REF - = GND The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3) CONDITIONS MIN GND - 0.3V GND - 0.3V -FS 0.5VREF FS/224 0.1 GND 0.1 11 11 11 -10 -10 -100 -100 1 1 1 1 50 120 10 10 100 100 VCC REF+ - 0.1V VCC V V V pF pF pF nA nA nA nA ns dB TYP MAX VCC + 0.3V VCC + 0.3V +FS UNITS V V V V DIGITAL INPUTS AND DIGITAL OUTPUTS SYMBOL VIH VIL VIH VIL IIN IIN CIN CIN VOH VOL VOH VOL IOZ PARAMETER High Level Input Voltage (CS, FO, SDI) Low Level Input Voltage (CS, FO, SDI) High Level Input Voltage (SCK) Low Level Input Voltage (SCK) Digital Input Current (CS, FO, SDI) Digital Input Current (SCK) Digital Input Capacitance (CS, FO, SDI) Digital Input Capacitance (SCK) High Level Output Voltage (SDO) Low Level Output Voltage (SDO) High Level Output Voltage (SCK) Low Level Output Voltage (SCK) Hi-Z Output Leakage (SDO) (Notes 10, 15) IO = -800A IO = 1.6mA CONDITIONS 2.7V VCC 5.5V 2.7V VCC 5.5V The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3) MIN TYP MAX 0.5 UNITS V V V V A A pF pF V VCC - 0.5 VCC - 0.5 0.5 -10 -10 10 10 10 10 2.7V VCC 5.5V (Notes 10, 15) 2.7V VCC 5.5V (Notes 10, 15) 0V VIN VCC 0V VIN VCC (Notes 10, 15) VCC - 0.5 0.4 VCC - 0.5 0.4 -10 10 V V V A IO = -800A (Notes 10, 17) IO = 1.6mA (Notes 10, 17) POWER REQUIREMENTS SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3) CONDITIONS MIN 2.7 TYP 160 200 1 MAX 5.5 275 300 2 UNITS V A A A 2492fb Conversion Current (Note 12) Temperature Measurement (Note 12) Sleep Mode (Note 12) 4 LTC2492 DIGITAL INPUTS AND DIGITAL OUTPUTS SYMBOL fEOSC tHEO tLEO tCONV_1 PARAMETER External Oscillator Frequency Range External Oscillator High Period External Oscillator Low Period Conversion Time for 1x Speed Mode 50Hz Mode 60Hz Mode Simultaneous 50/60Hz Mode External Oscillator 50Hz Mode 60Hz Mode Simultaneous 50/60Hz Mode External Oscillator Internal Oscillator (Notes 10, 17) External Oscillator (Notes 10, 11, 15) (Notes 10, 17) (Notes 10, 11, 15) (Notes 10, 11, 15) (Notes 10, 11, 15) Internal Oscillator (Notes 10, 17) External Oscillator (Notes 10, 11, 15) (Notes 10, 11, 15) The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3) CONDITIONS (Note 16) MIN 10 0.125 0.125 157.2 131 144.1 78.7 65.6 72.2 TYP MAX 4000 100 100 UNITS kHz s s ms ms ms ms ms ms ms ms kHz kHz 160.3 133.6 146.9 41036/fEOSC (in kHz) 80.3 66.9 73.6 20556/fEOSC (in kHz) 38.4 fEOSC/8 163.5 136.3 149.9 81.9 68.2 75.1 tCONV_2 Conversion Time for 2x Speed Mode fISCK DISCK fESCK tLESCK tHESCK tDOUT_ISCK tDOUT_ESCK t1 t2 t3 t4 tKQMAX tKQMIN t5 t7 t8 Internal SCK Frequency Internal SCK Duty Cycle External SCK Frequency Range External SCK Low Period External SCK High Period Internal SCK 32-Bit Data Output Time External SCK 32-Bit Data Output Time CS to SDO Low CS to SDO Hi-Z CS to SCK CS to SCK SCK to SDO Valid SDO Hold After SCK SCK Set-Up Before CS SDI Setup Before SCK SDI Hold After SCK 45 125 125 0.81 0.83 256/fEOSC (in kHz) 32/fESCK (in kHz) 0 0 0 50 55 4000 % kHz ns ns 0.85 ms ms ms ns ns ns ns ns ns ns ns ns 200 200 200 200 Internal SCK Mode External SCK Mode (Note 5) (Note 5) (Note 5) 15 50 100 100 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND. Note 3: Unless otherwise specified: VCC = 2.7V to 5.5V VREFCM = VREF /2, FS = 0.5VREF VIN = IN+ - IN -, VIN(CM) = (IN+ - IN -)/2, where IN+ and IN - are the selected input channels. Note 4: Use internal conversion clock or external conversion clock source with fEOSC = 307.2kHz unless other wise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: 50Hz mode (internal oscillator) or fEOSC = 256kHz 2% (external oscillator). Note 8: 60Hz mode (internal oscillator) or fEOSC = 307.2kHz 2% (external oscillator). Note 9: Simultaneous 50Hz/60Hz mode (internal oscillator) or fEOSC = 280kHz 2% (external oscillator). Note 10: The SCK can be configured in external SCK mode or internal SCK mode. In external SCK mode, the SCK pin is used as a digital input and the driving clock is fESCK . In the internal SCK mode, the SCK pin is used as a digital output and the output clock signal during the data output is fISCK . Note 11: The external oscillator is connected to the FO pin. The external oscillator frequency, fEOSC , is expressed in kHz. Note 12: The converter uses its internal oscillator. Note 13: The output noise includes the contribution of the internal calibration operations. Note 14: Guaranteed by design and test correlation. Note 15: The converter is in external SCK mode of operation such that the SCK pin is used as a digital input. The frequency of the clock signal driving SCK during the data output is fESCK and is expressed in Hz. Note 16: Refer to Applications Information section for performance vs data rate graphs. Note 17: The converter in internal SCK mode of operation such that the SCK pin is used as a digital output. 2492fb 5 LTC2492 TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity (VCC = 5V, VREF = 5V) 3 2 INL (ppm OF VREF) 1 0 85C -1 -2 -3 -2.5 -2 -1.5 -1 - 0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) VCC = 5V VREF = 5V VIN(CM) = 2.5V FO = GND INL (ppm OF VREF) -45C 25C 3 2 1 0 -1 -2 -3 -1.25 Integral Nonlinearity (VCC = 5V, VREF = 2.5V) 3 VCC = 5V VREF = 2.5V VIN(CM) = 1.25V FO = GND INL (ppm OF VREF) -45C, 25C, 90C 2 1 Integral Nonlinearity (VCC = 2.7V, VREF = 2.5V) VCC = 2.7V VREF = 2.5V VIN(CM) = 1.25V FO = GND -45C, 25C, 90C 0 -1 -2 -3 -1.25 2 2.5 -0.75 -0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2492 G02 -0.75 -0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2492 G03 2492 G01 Total Unadjusted Error (VCC = 5V, VREF = 5V) 12 8 TUE (ppm OF VREF) 4 0 -4 -8 -12 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) -45C VCC = 5V VREF = 5V VIN(CM) = 2.5V FO = GND 12 8 85C TUE (ppm OF VREF) 25C 4 0 -4 -8 Total Unadjusted Error (VCC = 5V, VREF = 2.5V) VCC = 5V VREF = 2.5V VIN(CM) = 1.25V FO = GND 12 85C 25C TUE (ppm OF VREF) 4 0 -4 -8 8 Total Unadjusted Error (VCC = 2.7V, VREF = 2.5V) VCC = 2.7V VREF = 2.5V VIN(CM) = 1.25V FO = GND 25C 85C -45C -45C 2 2.5 -12 -1.25 -0.75 -0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2492 G05 -12 -1.25 -0.75 -0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2492 G06 2492 G04 Noise Histogram (6.8sps) 14 12 NUMBER OF READINGS (%) 10,000 CONSECUTIVE READINGS RMS = 0.60V VCC = 5V AVERAGE = -0.69V VREF = 5V 10 VIN = 0V TA = 25C 8 6 4 2 0 -3 -2.4 -1.8 -1.2 -0.6 0 0.6 OUTPUT READING (V) 1.2 1.8 14 12 NUMBER OF READINGS (%) Noise Histogram (7.5sps) 10,000 CONSECUTIVE READINGS RMS = 0.59V VCC = 2.7V AVERAGE = -0.19V VREF = 2.5V 10 VIN = 0V TA = 25C 8 6 4 2 0 -3 -2.4 -1.8 -1.2 -0.6 0 0.6 OUTPUT READING (V) 1.2 1.8 5 Long-Term ADC Readings VCC = 5V, VREF = 5V, VIN = 0V, VIN(CM) = 2.5V 4 TA = 25C, RMS NOISE = 0.60V 3 ADC READING (V) 2 1 0 -1 -2 -3 -4 -5 0 10 30 40 20 TIME (HOURS) 50 60 2492 G09 2492 G07 2492 G08 2492fb 6 LTC2492 TYPICAL PERFORMANCE CHARACTERISTICS RMS Noise vs Input Differential Voltage 1.0 0.9 RMS NOISE (V) 0.8 0.7 0.6 0.5 0.4 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 INPUT DIFFERENTIAL VOLTAGE (V) VCC = 5V VREF = 5V VIN(CM) = 2.5V TA = 25C RMS NOISE (V) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 2.5 -1 0 1 2 3 4 5 6 2492 G11 RMS Noise vs VIN(CM) VCC = 5V VREF = 5V VIN = 0V TA = 25C RMS NOISE (V) 1.0 0.9 0.8 0.7 0.6 0.5 RMS Noise vs Temperature (TA) VCC = 5V VREF = 5V VIN = 0V VIN(CM) = GND 0.4 -45 -30 -15 VIN(CM) (V) 0 15 30 45 60 TEMPERATURE (C) 75 90 2492 G10 2492 G12 RMS Noise vs VCC 1.0 0.9 RMS NOISE (V) 0.8 0.7 0.6 0.5 0.4 2.7 1.0 VREF = 2.5V VIN = 0V VIN(CM) = GND TA = 25C RMS NOISE (V) 0.9 0.8 0.7 0.6 0.5 0.4 3.1 3.5 3.9 4.3 VCC (V) 4.7 5.1 5.5 RMS Noise vs VREF VCC = 5V VIN = 0V VIN(CM) = GND TA = 25C 0.3 0.2 0.1 0 -0.1 -0.2 Offset Error vs VIN(CM) VCC = 5V VREF = 5V VIN = 0V TA = 25C OFFSET ERROR (ppm OF VREF) -0.3 0 1 2 3 VREF (V) 4 5 2492 G14 -1 0 1 3 2 VIN(CM) (V) 4 5 6 2492 G15 2492 G13 Offset Error vs Temperature 0.3 0.2 0.1 0 0.3 VCC = 5V VREF = 5V VIN = 0V VIN(CM) = GND FO = GND 0.2 0.1 0 -0.1 -0.2 Offset Error vs VCC REF VIN = 0V VIN(CM) = GND TA = 25C REF+ = 2.5V - = GND 0.3 0.2 0.1 0 Offset Error vs VREF VCC = 5V REF - = GND VIN = 0V VIN(CM) = GND TA = 25C OFFSET ERROR (ppm OF VREF) OFFSET ERROR (ppm OF VREF) -0.1 -0.2 -0.3 -45 -30 -15 0 15 30 45 60 TEMPERATURE (C) 75 90 -0.3 2.7 3.1 3.5 3.9 4.3 VCC (V) 4.7 5.1 5.5 OFFSET ERROR (ppm OF VREF) -0.1 -0.2 -0.3 0 1 2 3 VREF (V) 4 5 2492 G18 2492 G16 2492 G17 2492fb 7 LTC2492 TYPICAL PERFORMANCE CHARACTERISTICS On-Chip Oscillator Frequency vs Temperature 310 310 On-Chip Oscillator Frequency vs VCC VREF = 2.5V VIN = 0V VIN(CM) = GND FO = GND TA = 25C 0 -20 -40 REJECTION (dB) -60 -80 -100 302 -120 -140 PSRR vs Frequency at VCC VCC = 4.1V DC VREF = 2.5V IN+ = GND IN- = GND FO = GND TA = 25C 308 FREQUENCY (kHz) FREQUENCY (kHz) 308 306 306 304 VCC = 4.1V VREF = 2.5V VIN = 0V VIN(CM) = GND FO = GND 0 15 30 45 60 TEMPERATURE (C) 75 90 304 302 300 -45 -30 -15 300 2.5 3.0 3.5 4.0 VCC (V) 4.5 5.0 5.5 2492 G20 1 10 10k 100k 1k 100 FREQUENCY AT VCC (Hz) 1M 2492 G19 2492 G21 PSRR vs Frequency at VCC 0 -20 -40 REJECTION (dB) -60 -80 -100 -120 -140 VCC = 4.1V DC 1.4V VREF = 2.5V IN+ = GND IN - = GND FO = GND TA = 25C 0 PSRR vs Frequency at VCC VCC = 4.1V DC 0.7V VREF = 2.5V -20 IN+ = GND IN- = GND -40 FO = GND TA = 25C -60 -80 -100 -120 -140 30600 200 Conversion Current vs Temperature FO = GND CS = GND SCK = NC SDO = NC SDI = GND CONVERSION CURRENT (A) 180 REJECTION (dB) VCC = 5V 160 VCC = 2.7V 140 120 0 20 40 60 80 100 120 140 160 180 200 220 FREQUENCY AT VCC (Hz) 2492 G22 30650 30750 FREQUENCY AT VCC (Hz) 30700 30800 2492 G23 100 -45 -30 -15 0 15 30 45 60 TEMPERATURE ( C) 75 90 2492 G24 Sleep Mode Current vs Temperature 2.0 FO = GND 1.8 CS = VCC SCK = NC 1.6 SDO = NC 1.4 SDI = GND 1.2 1.0 0.8 0.6 0.4 0.2 0 -45 -30 -15 0 15 30 45 60 TEMPERATURE (C) 75 90 150 100 VCC = 2.7V VCC = 5V 500 450 SUPPLY CURRENT (A) Conversion Current vs Output Data Rate VREF = VCC IN+ = GND IN - = GND 400 SCK = NC SDO = NC 350 SDI = GND CS GND F = EXT OSC 300 O TA = 25C 250 200 -2 3 2 INL (ppm OF VREF) VCC = 5V 1 0 -1 Integral Nonlinearity (2x Speed Mode; VCC = 5V, VREF = 5V) VCC = 5V VREF = 5V VIN(CM) = 2.5V FO = GND SLEEP MODE CURRENT (A) 25C, 90C VCC = 3V - 45C 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2492 G26 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) 2 2.5 2492 G25 2492 G27 2492fb 8 LTC2492 TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity (2x Speed Mode; VCC = 5V, VREF = 2.5V) 3 2 INL (ppm OF VREF) 1 90C 0 -1 -2 -3 -1.25 -45C, 25C VCC = 5V VREF = 2.5V VIN(CM) = 1.25V FO = GND INL (ppm OF VREF) 3 2 1 90C 0 -1 -2 -3 -1.25 -45C, 25C Integral Nonlinearity (2x Speed Mode; VCC = 2.7V, VREF = 2.5V) VCC = 2.7V VREF = 2.5V VIN(CM) = 1.25V FO = GND 16 Noise Histogram (2x Speed Mode) RMS = 0.85V 10,000 CONSECUTIVE AVERAGE = 0.184mV 14 READINGS VCC = 5V 12 VREF = 5V VIN = 0V T = 25C 10 A 8 6 4 2 NUMBER OF READINGS (%) -0.75 -0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2492 G28 -0.75 -0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2492 G29 0 179 181.4 183.8 186.2 OUTPUT READING (V) 188.6 2492 G30 RMS Noise vs VREF (2x Speed Mode) 1.0 200 198 0.8 OFFSET ERROR (V) RMS NOISE (V) 196 194 192 190 188 186 184 182 180 3 2 VREF (V) 4 5 2492 G31 Offset Error vs VIN(CM) (2x Speed Mode) VCC = 5V VREF = 5V VIN = 0V FO = GND TA = 25C 240 230 OFFSET ERROR (V) 220 210 200 190 180 170 -1 0 1 3 VIN(CM) (V) 2 4 5 6 2492 G32 Offset Error vs Temperature (2x Speed Mode) VCC = 5V VREF = 5V VIN = 0V VIN(CM) = GND FO = GND 0.6 0.4 VCC = 5V VIN = 0V VIN(CM) = GND FO = GND TA = 25C 0 1 0.2 0 160 -45 -30 -15 0 15 30 45 60 TEMPERATURE (C) 75 90 2492 G33 2492fb 9 LTC2492 TYPICAL PERFORMANCE CHARACTERISTICS Offset Error vs VCC (2x Speed Mode) 250 VREF = 2.5V VIN = 0V VIN(CM) = GND FO = GND TA = 25C 240 230 OFFSET ERROR (V) 220 210 200 190 180 170 0 2 2.5 3 4 3.5 VCC (V) 4.5 5 5.5 2492 G34 Offset Error vs VREF (2x Speed Mode) 0 VCC = 5V VIN = 0V VIN(CM) = GND FO = GND TA = 25C -20 -40 REJECTION (dB) -60 -80 -100 -120 -140 0 1 2 3 VREF (V) 4 5 2492 G35 PSRR vs Frequency at VCC (2x Speed Mode) VCC = 4.1V DC REF + = 2.5V REF - = GND IN+ = GND IN- = GND FO = GND TA = 25C 200 OFFSET ERROR (V) 150 100 50 160 1 10 10k 100k 1k 100 FREQUENCY AT VCC (Hz) 1M 2492 G36 PSRR vs Frequency at VCC (2x Speed Mode) 0 -20 -40 -60 -80 -100 -120 -140 VCC = 4.1V DC 1.4V REF + = 2.5V REF - = GND IN + = GND IN - = GND FO = GND TA = 25C 0 -20 PSRR vs Frequency at VCC (2x Speed Mode) VCC = 4.1V DC 0.7V REF + = 2.5V REF - = GND IN+ = GND -40 IN- = GND FO = GND -60 TA = 25C -80 -100 -120 -140 30600 RREJECTION (dB) REJECTION (dB) 0 20 40 60 80 100 120 140 160 180 200 220 FREQUENCY AT VCC (Hz) 2492 G37 30650 30700 30750 FREQUENCY AT VCC (Hz) 30800 2492 G38 2492fb 10 LTC2492 PIN FUNCTIONS FO (Pin 1): Frequency Control Pin. Digital input that controls the internal conversion clock rate. When FO is connected to GND, the converter uses its internal oscillator running at 307.2kHz. The conversion clock may also be overridden by driving the FO pin with an external clock in order to change the output rate and the digital filter rejection null. SDI (Pin 2): Serial Data Input. This pin is used to select the line frequency rejection mode, 1x or 2x speed mode, temperature sensor, as well as the input channel. The serial data input is applied under control of the serial clock (SCK) during the data output/input operation. The first conversion following a new input or mode change is valid. SCK (Pin 3): Bidirectional, Digital I/O, Clock Pin. In Internal Serial Clock Operation mode, SCK is generated internally and is seen as an output on the SCK pin. In External Serial Clock Operation mode, the digital I/O clock is externally applied to the SCK pin. The Serial Clock operation mode is determined by the logic level applied to the SCK pin at power up and during the most recent falling edge of CS. CS (Pin 4): Active LOW Chip Select. A LOW on this pin enables the digital input/output and wakes up the ADC. Following each conversion, the ADC automatically enters the Sleep mode and remains in this low power state as long as CS is HIGH. A LOW-to-HIGH transition on CS during the data output aborts the data transfer and starts a new conversion. SDO (Pin 5): Three-State Digital Output. During the data output period, this pin is used as the serial data output. When the chip select pin is HIGH, the SDO pin is in a high impedance state. During the conversion and sleep periods, this pin is used as the conversion status output. When the conversion is in progress this pin is HIGH; once the conversion is complete SDO goes low. The conversion status is monitored by pulling CS LOW. GND (Pin 6): Ground. Connect this pin to a common ground plane through a low impedance connection. COM (Pin 7): The common negative input (IN -) for all single-ended multiplexer configurations. The voltage on CH0 to CH3 and COM pins can have any value between GND - 0.3V to VCC + 0.3V. Within these limits, the two selected inputs (IN+ and IN -) provide a bipolar input range (VIN = IN+ - IN -) from -0.5 * VREF to 0.5 * VREF . Outside this input range, the converter produces unique over-range and under-range output codes. CH0 to CH3 (Pins 8-11): Analog Inputs. May be programmed for single-ended or differential mode. VCC (Pin 12): Positive Supply Voltage. Bypass to GND with a 10F tantalum capacitor in parallel with a 0.1F ceramic capacitor as close to the part as possible. REF+ (Pin 13), REF - (Pin 14): Differential Reference Input. The voltage on these pins can have any value between GND and VCC as long as the reference positive input, REF+, remains more positive than the negative reference input, REF -, by at least 0.1V. The differential voltage (VREF = REF+ - REF -) sets the fullscale range for all input channels. When performing an on-chip temperature measurement, the minimum value of REF = 2V. Exposed Pad (Pin 15): Ground. This pin is ground and must be soldered to the PCB ground plane. For prototyping purposes, this pin may remain floating. 2492fb 11 LTC2492 FUNCTIONAL BLOCK DIAGRAM VCC GND REF + REF - CH0 CH1 CH2 CH3 COM IN + MUX IN - TEMP SENSOR AUTOCALIBRATION AND CONTROL INTERNAL OSCILLATOR FO (INT/EXT) - + SERIAL INTERFACE DECIMATING FIR ADDRESS 2492 BD DIFFERENTIAL 3RD ORDER MODULATOR SDI SCK SDO CS Figure 1. Functional Block Diagram TEST CIRCUITS VCC 1.69k SDO 1.69k CLOAD = 20pF SDO CLOAD = 20pF Hi-Z TO VOH VOL TO VOH VOH TO Hi-Z 2492 TC01 Hi-Z TO VOL VOH TO VOL VOL TO Hi-Z 2492 TC02 2492fb 12 LTC2492 TIMING DIAGRAMS Timing Diagram Using Internal SCK (SCK HIGH with CS) CS t1 SDO Hi-Z t3 SCK t7 SDI SLEEP DATA IN/OUT CONVERSION 2492 TD01 t2 Hi-Z tKQMIN tKQMAX t8 Timing Diagram Using External SCK (SCK LOW with CS) CS t1 SDO Hi-Z t5 t4 SCK t7 SDI SLEEP DATA IN/OUT CONVERSION 2492 TD02 t2 Hi-Z tKQMIN tKQMAX t8 2492fb 13 LTC2492 APPLICATIONS INFORMATION CONVERTER OPERATION Converter Operation Cycle The LTC2492 is a multi-channel, low power, deltasigma analog-to-digital converter with an easy to use 4-wire interface and automatic differential input current cancellation. Its operation is made up of four states (See Figure 2). The converter operating cycle begins with the conversion, followed by the sleep state and ends with the data input/output cycle. The 4-wire interface consists of serial data output (SDO), serial clock (SCK), chip select (CS) and serial data input (SDI).The interface, timing, operation cycle, and data output format is compatible with Linear's entire family of SPI converters. Initially, at power up, the LTC2492 performs a conversion. Once the conversion is complete, the device enters the sleep state. While in this sleep state, if CS is HIGH, power consumption is reduced by two orders of magnitude. The part remains in the sleep state as long as CS is HIGH. The conversion result is held indefinitely in a static shift register while the part is in the sleep state. Once CS is pulled LOW, the device powers up, exits the sleep state, and enters the data input/output state. If CS is brought HIGH before the first rising edge of SCK, the device returns to the sleep state and the power is reduced. If CS is brought HIGH after the first rising edge of SCK, the POWER UP IN+= CH0, IN-= CH1 50/60Hz,1X data output cycle is aborted and a new conversion cycle begins. The data output corresponds to the conversion just completed. This result is shifted out on the serial data output pin (SDO) under the control of the serial clock pin (SCK). Data is updated on the falling edge of SCK allowing the user to reliably latch data on the rising edge of SCK (See Figure 3). The configuration data for the next conversion is also loaded into the device at this time. Data is loaded from the serial data input pin (SDI) on each rising edge of SCK. The data input/output cycle concludes once 32 bits are read out of the ADC or when CS is brought HIGH. The device automatically initiates a new conversion and the cycle repeats. Through timing control of the CS and SCK pins, the LTC2492 offers several flexible modes of operation (internal or external SCK and free-running conversion modes). These various modes do not require programming and do not disturb the cyclic operation described above. These modes of operation are described in detail in the Serial Interface Timing Modes section. Ease of Use The LTC2492 data output has no latency, filter settling delay, or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog inputs is straight forward. Each conversion, immediately following a newly selected input or mode, is valid and accurate to the full specifications of the device. The LTC2492 automatically performs offset and full scale calibration every conversion cycle independent of the input channel selected. This calibration is transparent to the user and has no effect with the operation cycle described above. The advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage variation, input channel, and temperature drift. CONVERT SLEEP CS = LOW AND SCK CHANNEL SELECT CONFIGURATION SELECT DATA OUTPUT 2492 F02 Figure 2. LTC2492 State Transition Diagram 2492fb 14 LTC2492 APPLICATIONS INFORMATION Easy Drive Input Current Cancellation The LTC2492 combines a high precision delta-sigma ADC with an automatic, differential, input current cancellation front end. A proprietary front end passive sampling network transparently removes the differential input current. This enables external RC networks and high impedance sensors to directly interface to the LTC2492 without external amplifiers. The remaining common mode input current is eliminated by either balancing the differential input impedances or setting the common mode input equal to the common mode reference (see Automatic Differential Input Current Cancellation Section). This unique architecture does not require on-chip buffers, thereby enabling signals to swing beyond ground and VCC . Moreover, the cancellation does not interfere with the transparent offset and full-scale auto-calibration and the absolute accuracy (full scale + offset + linearity + drift) is maintained even with external RC networks. Power-Up Sequence The LTC2492 automatically enters an internal reset state when the power supply voltage VCC drops below approximately 2V. This feature guarantees the integrity of the conversion result, input channel selection, and serial clock mode. When VCC rises above this threshold, the converter creates an internal power-on-reset (POR) signal with a duration of approximately 4ms. The POR signal clears all internal registers. The conversion immediately following a POR cycle is performed on the input channel IN+ = CH0, IN - = CH1, simultaneous 50Hz/60Hz rejection and 1x output rate. The first conversion following a POR cycle is accurate within the specification of the device if the power supply voltage is restored to (2.7V to 5.5V) before the end of the POR interval. A new input channel, rejection mode, speed mode, or temperature selection can be programmed into the device during this first data input/output cycle. Reference Voltage Range This converter accepts a truly differential external reference voltage. The absolute/common mode voltage range for REF+ and REF - pins covers the entire operating range of the device (GND to VCC). For correct converter operation, VREF must be positive (REF+ > REF -). The LTC2492 differential reference input range is 0.1V to VCC . For the simplest operation, REF + can be shorted to VCC and REF- can be shorted to GND. The converter output noise is determined by the thermal noise of the front end circuits, and as such, its value in nanovolts is nearly constant with reference voltage. A decrease in reference voltage will not significantly improve the converter's effective resolution. On the other hand, a decreased reference will improve the converter's overall INL performance. Input Voltage Range The analog inputs are truly differential with an absolute, common mode range for the CH0 to CH3 and COM input pins extending from GND - 0.3V to VCC + 0.3V. Outside these limits, the ESD protection devices begin to turn on and the errors due to input leakage current increase rapidly. Within these limits, the LTC2492 converts the bipolar differential input signal VIN = IN + - IN - (where IN+ and IN- are the selected input channels), from -FS = -0.5 * VREF to +FS = 0.5 * VREF where VREF = REF + - REF -. Outside this range, the converter indicates the overrange or the underrange condition using distinct output codes (see Table 1). Signals applied to the input (CH0 to CH3, COM) may extend 300mV below ground and above VCC . In order to limit any fault current, resistors of up to 5k may be added in series with the input. The effect of series resistance on the converter accuracy can be evaluated from the curves presented in the Input Current/Reference Current sections. In addition, series resistors will introduce a temperature dependent error due to input leakage current. A 1nA input leakage current will develop a 1ppm offset error on a 5k resistor if VREF = 5V. This error has a very strong temperature dependency. 2492fb 15 LTC2492 APPLICATIONS INFORMATION SERIAL INTERFACE PINS The LTC2492 transmits the conversion result, reads the input configuration, and receives a start of conversion command through a synchronous 3- or 4-wire interface. During the conversion and sleep states, this interface can be used to access the converter status. During the data output state, it is used to read the conversion result, program the input channel, rejection frequency, speed multiplier, and select the temperature sensor. Serial Clock Input/Output (SCK) The serial clock pin (SCK) is used to synchronize the data input/output transfer. Each bit is shifted out of the SDO pin on the falling edge of SCK and data is shifted into the SDI pin on the rising edge of SCK. The serial clock pin (SCK) can be configured as either a master (SCK is an output generated internally) or a slave (SCK is an input and applied externally). Master mode (Internal SCK) is selected by simply floating the SCK pin. Slave mode (External SCK) is selected by driving SCK low during power up and each falling edge of CS. Specific details of these SCK modes are described in the Serial Interface Timing Modes section. Serial Data Output (SDO) The serial data output pin (SDO) provides the result of the last conversion as a serial bit stream (MSB first) during the data output state. In addition, the SDO pin is used as an end of conversion indicator during the conversion and sleep states. When CS is HIGH, the SDO driver is switched to a high impedance state in order to share the data output line with other devices. If CS is brought LOW during the conversion phase, the EOC bit (SDO pin) will be driven HIGH. Once the conversion is complete, if CS is brought LOW, EOC will be driven LOW indicating the conversion is complete and the result is ready to be shifted out of the device. Chip Select (CS) The active low CS pin is used to test the conversion status, enable I/O data transfer, initiate a new conversion, control 2492fb the duration of the sleep state, and set the SCK mode. At the conclusion of a conversion cycle, while CS is HIGH, the device remains in a low power sleep state where the supply current is reduced several orders of magnitude. In order to exit the sleep state and enter the data output state, CS must be pulled low. Data is now shifted out the SDO pin under control of the SCK pin as described previously. A new conversion cycle is initiated either at the conclusion of the data output cycle (all 32 data bits read) or by pulling CS HIGH any time between the first and 32nd rising edges of the serial clock (SCK). In this case, the data output is aborted and a new conversion begins. Serial Data Input (SDI) The serial data input (SDI) is used to select the input channel, rejection frequency, speed multiplier and to access the integrated temperature sensor. Data is shifted into the device during the data output/input state on the rising edge of SCK while CS is low. OUTPUT DATA FORMAT The LTC2492 serial output stream is 32 bits long. The first bit indicates the conversion status, the second bit is always zero, and the third bit conveys sign information. The next 24 bits are the conversion result, MSB first. The remaining 5 bits are sub LSBs beyond the 24-bit level that may be included in averaging or discarded without loss of resolution. Bit 31 (first output bit) is the end of conversion (EOC) indicator. This bit is available on the SDO pin during the conversion and sleep states whenever CS is LOW. This bit is HIGH during the conversion cycle, goes LOW once the conversion is complete, and is HI-Z when CS is HIGH. Bit 30 (second output bit) is a dummy bit (DMY) and is always LOW. Bit 29 (third output bit) is the conversion result sign indicator (SIG). If the selected input (VIN = IN+ - IN -) is greater than 0V, this bit is HIGH. If VIN < 0, this bit is LOW. 16 LTC2492 APPLICATIONS INFORMATION Bit 28 (fourth output bit) is the most significant bit (MSB) of the result. This bit in conjunction with Bit 29 also provides underrange and overrange indication. If both Bit 29 and Bit 28 are HIGH, the differential input voltage is above +FS. If both Bit 29 and Bit 28 are LOW, the differential input voltage is below -FS. The function of these bits is summarized in Table 1. Table 1. LTC2492 Status Bits Input Range VIN 0.5 * VREF 0V VIN < 0.5 * VREF -0.5 * VREF VIN < 0V VIN < -0.5 * VREF Bit 31 EOC 0 0 0 0 Bit 30 DMY 0 0 0 0 Bit 29 SIG 1 1 0 0 Bit 28 MSB 1 0 1 0 an external microcontroller. Bit 31 (EOC) can be captured on the first rising edge of SCK. Bit 30 is shifted out of the device on the first falling edge of SCK. The final data bit (Bit 0) is shifted out on the on the falling edge of the 31st SCK and may be latched on the rising edge of the 32nd SCK pulse. On the falling edge of the 32nd SCK pulse, SDO goes HIGH indicating the initiation of a new conversion cycle. This bit serves as EOC (Bit 31) for the next conversion cycle. Table 2 summarizes the output data format. As long as the voltage on the IN+ and IN - pins remains between -0.3V and VCC + 0.3V (absolute maximum operating range) a conversion result is generated for any differential input voltage VIN from -FS = -0.5 * VREF to +FS = 0.5 * VREF . For differential input voltages greater than +FS, the conversion result is clamped to the value corresponding to +FS + 1LSB. For differential input voltages below -FS, the conversion result is clamped to the value -FS - 1LSB. INPUT DATA FORMAT The LTC2492 serial input word is 13 bits long and contains two distinct sets of data. The first set (SGL, ODD, A2, A1, A0) is used to select the input channel. The second set of data (IM, FA, FB, SPD) is used to select the frequency rejection, speed mode (1x, 2x), and temperature measurement. After power up, the device initiates an internal reset cycle which sets the input channel to CH0 to CH1 (IN+ = CH0, IN- = CH1), the frequency rejection to simultaneous 50Hz/60Hz, and 1x output rate (auto-calibration enabled). The first Bits 28 to 5 are the 24-bit conversion result MSB first. Bit 5 is the least significant bit (LSB24). Bits 4 to 0 are sub LSBs below the 24-bit level. Bits 4 to 0 may be included in averaging or discarded without loss of resolution. Data is shifted out of the SDO pin under control of the serial clock (SCK) (see Figure 3). Whenever CS is HIGH, SDO remains high impedance and SCK is ignored. In order to shift the conversion result out of the device, CS must first be driven LOW. EOC is seen at the SDO pin of the device once CS is pulled LOW. EOC changes in real time as a function of the internal oscillator or the clock applied to the fO pin from HIGH to LOW at the completion of a conversion. This signal may be used as an interrupt for CS 1 SCK (EXTERNAL) 2 3 4 5 6 7 8 9 10 11 12 13 14 32 SDI DON'T CARE 1 0 EN SGL ODD A2 A1 A0 EN2 IM FA FB SPD DON'T CARE SDO EOC "0" SIG MSB BIT 0 BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 CONVERSION SLEEP DATA INPUT/OUTPUT 2492 F03 Figure 3. Channel Selection, Configuration Selection and Data Output Timing 2492fb 17 LTC2492 APPLICATIONS INFORMATION Table 2. Output Data Format Differential Input Voltage VIN* VIN* 0.5 * VREF** 0.5 * VREF** - 1LSB 0.25 * VREF** 0.25 * VREF** - 1LSB 0 -1LSB -0.25 * VREF** -0.25 * VREF** - 1LSB -0.5 * VREF** VIN* < -0.5 * VREF** Bit 31 EOC 0 0 0 0 0 0 0 0 0 0 Bit 30 DMY 0 0 0 0 0 0 0 0 0 0 Bit 29 SIG 1 1 1 1 1 0 0 0 0 0 Bit 28 MSB 1 0 0 0 0 1 1 1 1 0 Bit 27 0 1 1 0 0 1 1 0 0 1 Bit 26 0 1 0 1 0 1 0 1 0 1 Bit 25 0 1 0 1 0 1 0 1 0 1 ... ... ... ... ... ... ... ... ... ... ... Bit 5 LSB 0 1 0 1 0 1 0 1 0 1 Bits 4 to 0 SUB LSBs 00000 XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX 11111 *The differential input voltage VIN = IN+ - IN-. **The differential reference voltage VREF = REF+ - REF-. ** Sub LSBs are below the 24-bit level. They may be included in averaging, or discarded without loss of resolution. conversion automatically begins at power up using this default configuration. Once the conversion is complete, a new word may be written into the device. The first three bits shifted into the device consist of two preamble bits and an enable bit. These bits are used to enable the device configuration and input channel selection. Valid settings for these three bits are 000, 100 and 101. Other combinations should be avoided. If the first three bits are 000 or 100, the following data is ignored (don't care) and the previously selected input channel and configuration remain valid for the next conversion. If the first three bits shifted into the device are 101, then the next five bits select the input channel for the next conversion cycle (see Table 3). Table 3 Channel Selection MUX ADDRESS SGL *0 0 0 0 1 1 1 1 ODD/ SIGN 0 0 1 1 0 0 1 1 A2 0 0 0 0 0 0 0 0 A1 0 0 0 0 0 0 0 0 A0 0 1 0 1 0 1 0 1 IN+ IN+ IN+ IN+ IN - IN+ IN - IN+ IN - IN - IN - IN - 0 IN+ CHANNEL SELECTION 1 IN - IN+ IN - 2 3 COM The first input bit (SGL) following the 101 sequence determines if the input selection is differential (SGL = 0) or single-ended (SGL = 1). For SGL = 0, two adjacent channels can be selected to form a differential input. For SGL = 1, one of four channels is selected as the positive input. The negative input is COM for all single-ended operations. The remaining four bits (ODD, A2, A1, A0) determine which channel(s) is/are selected and the polarity (for a differential input). The next serial input bit immediately following the input channel selection is the enable bit for the conversion configuration (EN2). If this bit is set to 0, then the next conversion is performed using the previously selected converter configuration. A new configuration can be loaded into the device by setting EN2 = 1 (see Table 4). The first bit (IM) is used to select the internal temperature sensor. If IM = 1, the following conversion will be performed on the internal temperature sensor rather than the selected input channel. The next two bits (FA and FB) are used to set the rejection frequency. The final bit (SPD) is used to select either the 1x output rate if SPD = 0 (auto-calibration is enabled and the offset is continuously calibrated and removed from the final conversion result) or the 2x output rate if SPD = 1 (offset calibration disabled, multiplexing output rates up to 15Hz with no latency). When IM = 1 (temperature measurement) SPD will be ignored and the device will operate in 1x mode. The configuration remains valid until 2492fb *Default at power up 18 LTC2492 APPLICATIONS INFORMATION Table 4. Converter Configuration 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN 0 1 0 1 1 1 1 1 1 1 1 1 1 SGL X X X X X X X X X X X X X ODD X X X X X X X X X X X X X A2 X X X X X X X X X X X X X A1 X X X X X X X X X X X X X A0 X X X X X X X X X X X X X EN2 X 0 X 1 1 1 1 1 1 1 1 1 1 IM X X X 0 0 0 0 0 0 1 1 1 X FA X X X 0 0 1 0 0 1 0 0 1 1 FB X X X 0 1 0 0 1 0 0 1 0 1 SPD X X X 0 0 0 1 1 1 X X X X CONVERTER CONFIGURATION Keep Previous Keep Previous Keep Previous External Input (See Table 3) 50Hz/60Hz Rejection, 1x External Input (See Table 3) 50Hz Rejection, 1x External Input (See Table 3) 60Hz Rejection, 1x External Input (See Table 3) 50Hz/60Hz Rejection, 2x External Input (See Table 3) 50Hz Rejection, 2x External Input (See Table 3) 60Hz Rejection, 2x Measure Temperature 50Hz/60Hz Rejection, 1x Measure Temperature 50Hz Rejection, 1x Measure Temperature 60Hz Rejection, 1x Reserved, Do Not Use a new input word with EN = 1 (the first three bits are 101) and EN2 = 1 is shifted into the device. Rejection Mode (FA, FB) The LTC2492 includes a high accuracy on-chip oscillator with no required external components. Coupled with an integrated 4th order digital low pass filter, the LTC2492 rejects line frequency noise. In the default mode, the LTC2492 simultaneously rejects 50Hz and 60Hz by at least 87dB. If more rejection is required, the LTC2492 can be configured to reject 50Hz or 60Hz to better than 110dB. Speed Mode (SPD) Every conversion cycle, two conversions are combined to remove the offset (default mode). This result is free from offset and drift. In applications where the offset is not critical, the auto-calibration feature can be disabled with the benefit of twice the output rate. While operating in the 2x mode (SPD = 1), the linearity and full-scale errors are unchanged from the 1x mode performance. In both the 1x and 2x mode there is no latency. This enables input steps or multiplexer changes to settle in a single conversion cycle, easing system overhead and increasing the effective conversion rate. During temperature measurements, the 1x mode is always used independent of the value of SPD. Temperature Sensor The LTC2492 includes an integrated temperature sensor. The temperature sensor is selected by setting IM = 1. The digital output is proportional to the absolute temperature of the device. This feature allows the converter to perform cold junction compensation for external thermocouples or continuously remove the temperature effects of external sensors. The internal temperature sensor output is 28mV at 27C (300K), with a slope of 93.5V/C independent of VREF (see Figures 4 and 5). Slope calibration is not required if the reference voltage (VREF) is known. A 5V reference has a slope of 314 LSBs24/C. The temperature is calculated 2492fb 19 LTC2492 APPLICATIONS INFORMATION from the output code (DATAOUT24) for a 5V reference using the following formula: TK = DATAOUT24/314 in Kelvin If a different value of VREF is used, the temperature output is: TK = DATAOUT24 * VREF/1570 in Kelvin If the value of VREF is not known, the slope is determined by measuring the temperature sensor at a known temperature TN (in K) and using the following formula: SLOPE = DATAOUT24/TN This value of slope can be used to calculate further temperature readings using: TK = DATAOUT24/SLOPE 140000 All Kelvin temperature readings can be converted to TC (C) using the fundamental equation: TC = TK - 273 SERIAL INTERFACE TIMING MODES The LTC2492's 4-wire interface is SPI and MICROWIRE compatible. This interface offers several flexible modes of operation. These include internal/external serial clock, 3- or 4-wire I/O, single cycle or continuous conversion. The following sections describe each of these timing modes in detail. In all cases, the converter can use the internal oscillator (FO = LOW) or an external oscillator connected to the FO pin. For each mode, the operating cycle, data input format, data output format, and performance remain the same. Refer to Table 5 for a summary. 5 4 3 ABSOLUTE ERROR (C) 2 1 0 -1 -2 -3 VCC = 5V VREF = 5V 120000 SLOPE = 314 LSB /K 24 100000 DATAOUT24 80000 60000 40000 20000 0 -4 0 100 200 300 TEMPERATURE (K) 400 2492 F04 -5 -55 -30 -5 20 45 70 TEMPERATURE (C) 95 120 2492 F05 Figure 4. Internal PTAT Digital Output vs Temperature Figure 5. Absolute Temperature Error Table 5. Serial Interface Timing Modes CONFIGURATION External SCK, Single Cycle Conversion External SCK, 3-Wire I/O Internal SCK, Single Cycle Conversion Internal SCK, 3-Wire I/O, Continuous Conversion SCK CONVERSION DATA OUTPUT CONNECTION AND SOURCE CYCLE CONTROL CONTROL WAVEFORMS External External Internal Internal CS and SCK SCK CS Continuous CS and SCK SCK CS Internal Figures 6, 7 Figure 8 Figures 9, 10 Figure 11 2492fb 20 LTC2492 APPLICATIONS INFORMATION External Serial Clock, Single Cycle Operation This timing mode uses an external serial clock to shift out the conversion result and CS to monitor and control the state of the conversion cycle (see Figure 6). The external serial clock mode is selected during the powerup sequence and on each falling edge of CS. In order to enter and remain in the external SCK mode of operation, SCK must be driven LOW both at power up and on each CS falling edge. If SCK is HIGH on the falling edge of CS, the device will switch to the internal SCK mode. The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. While CS is LOW, EOC is output to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the conversion is complete and the device is in the sleep state. Independent of CS, the device automatically enters the sleep state once the conversion is complete; however, in order to reduce the power, CS must be HIGH. 2.7V TO 5.5V 12 10F REFERENCE VOLTAGE 0.1V TO VCC 13 14 8 9 ANALOG INPUTS 10 11 7 VCC LTC2492 REF + REF - CH0 CH1 CH2 CH3 COM GND 6 CS SDO 5 4 SDI SCK 2 3 4-WIRE SPI INTERFACE FO 1 = EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR When the device is in the sleep state, its conversion result is held in an internal static shift register. The device remains in the sleep state until the first rising edge of SCK is seen while CS is LOW. The input data is then shifted in via the SDI pin on each rising edge of SCK (including the first rising edge). The channel selection and converter configuration mode will be used for the following conversion cycle. If the input channel or converter configuration is changed during this I/O cycle, the new settings take effect on the conversion cycle following the data input/output cycle. The output data is shifted out the SDO pin on each falling edge of SCK. This enables external circuitry to latch the output on the rising edge of SCK. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 32nd rising edge of SCK. On the 32nd falling edge of SCK, the device begins a new conversion and SDO goes HIGH (EOC = 1) indicating a conversion is in progress. At the conclusion of the data cycle, CS may remain LOW and EOC monitored as an end-of-conversion interrupt. 0.1F CS 1 SCK (EXTERNAL) 2 3 4 5 6 7 8 9 10 11 12 13 14 32 SDI DON'T CARE 1 0 EN SGL ODD A2 A1 A0 EN2 IM FA FB SPD DON'T CARE SDO EOC "0" SIG MSB BIT 20 BIT 19 BIT 18 BIT 17 BIT 0 Hi-Z BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 CONVERSION SLEEP DATA INPUT/OUTPUT CONVERSION 2492 F06 Figure 6. External Serial Clock, Single Cycle Operation 2492fb 21 LTC2492 APPLICATIONS INFORMATION Typically, CS remains LOW during the data output/input state. However, the data output state may be aborted by pulling CS HIGH any time between the 1st falling edge and the 32nd falling edge of SCK (see Figure 7). On the rising edge of CS, the device aborts the data output state and immediately initiates a new conversion. In order to program a new input channel, 8 SCK clock pulses are required. If the data output sequence is aborted prior to the 8th falling edge of SCK, the new input data is ignored and the previously selected input channel remains valid. If the rising edge of CS occurs after the 8th falling edge of SCK, the new input channel is loaded and valid for the next conversion cycle. If CS goes high between the 8th falling edge and the 16th falling edge of SCK, the new channel is still loaded, but the converter configuration remains unchanged. In order to program both the input channel and converter configuration, CS must go high after the 16th falling edge of SCK (at this point all data has been shifted into the device). 2.7V TO 5.5V 12 10F REFERENCE VOLTAGE 0.1V TO VCC 13 14 8 9 ANALOG INPUTS 10 11 7 VCC LTC2492 REF + REF - External Serial Clock, 3-Wire I/O This timing mode uses a 3-wire serial I/O interface. The conversion result is shifted out of the device by an externally generated serial clock (SCK) signal (see Figure 8). CS is permanently tied to ground, simplifying the user interface or isolation barrier. The external serial clock mode is selected at the end of the power-on reset (POR) cycle. The POR cycle typically concludes 4ms after VCC exceeds 2V. The level applied to SCK at this time determines if SCK is internally generated or externally applied. In order to enter the external SCK mode, SCK must be driven LOW prior to the end of the POR cycle. Since CS is tied LOW, the end-of-conversion (EOC) can be continuously monitored at the SDO pin during the convert and sleep states. EOC may be used as an interrupt to an external controller. EOC = 1 while the conversion is in progress and EOC = 0 once the conversion is complete. FO 1 = EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR SDI SCK 2 3 4-WIRE SPI INTERFACE 0.1F CH0 CH1 CH2 CH3 COM GND 6 CS SDO 5 4 CS 1 SCK (EXTERNAL) 2 3 4 5 6 7 8 SDI DON'T CARE 1 0 EN SGL ODD A2 A1 A0 DON'T CARE SDO EOC "0" SIG MSB BIT 23 Hi-Z BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 CONVERSION SLEEP DATA INPUT/OUTPUT CONVERSION SLEEP 2492 F07 Figure 7. External Serial Clock, Reduced Output Data Length and Valid Channel Selection 2492fb 22 LTC2492 APPLICATIONS INFORMATION 2.7V TO 5.5V 12 10F REFERENCE VOLTAGE 0.1V TO VCC 13 14 8 9 ANALOG INPUTS 10 11 7 VCC LTC2492 REF + REF - FO 1 = EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR SDI SCK 5 2 3 3-WIRE SPI INTERFACE 0.1F CH0 CH1 CH2 CH3 COM GND 6 SDO CS 4 CS 1 SCK (EXTERNAL) 2 3 4 5 6 7 8 9 10 11 12 13 14 32 SDI DON'T CARE 1 0 EN SGL ODD A2 A1 A0 EN2 IM FA FB SPD DON'T CARE SDO EOC "0" SIG MSB BIT 20 BIT 19 BIT 18 BIT 17 BIT 0 CONVERSION 2492 F08 BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 CONVERSION SLEEP DATA INPUT/OUTPUT Figure 8. External Serial Clock, 3-Wire Operation (CS = 0) On the falling edge of EOC, the conversion result is loading into an internal static shift register. The output data can now be shifted out the SDO pin under control of the externally applied SCK signal. Data is updated on the falling edge of SCK. The input data is shifted into the device through the SDI pin on the rising edge of SCK. On the 32nd falling edge of SCK, SDO goes HIGH, indicating a new conversion has begun. This data now serves as EOC for the next conversion. Internal Serial Clock, Single Cycle Operation This timing mode uses the internal serial clock to shift out the conversion result and CS to monitor and control the state of the conversion cycle (see Figure 9). In order to select the internal serial clock timing mode, the serial clock pin (SCK) must be floating or pulled HIGH before the conclusion of the POR cycle and prior to each falling edge of CS. An internal weak pull-up resistor is active on the SCK pin during the falling edge of CS; therefore, the internal SCK mode is automatically selected if SCK is not externally driven. The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled low in order to monitor the state of the converter. Once CS is pulled LOW, SCK goes LOW and EOC is output to the SDO pin. EOC = 1 while the conversion is in progress and EOC = 0 if the device is in the sleep state. When testing EOC, if the conversion is complete (EOC = 0), the device will exit sleep state. In order to return to the sleep state and reduce the power consumption, CS must be pulled HIGH before the device pulls SCK HIGH. When the device is using its own internal oscillator (FO is tied LOW), the first rising edge of SCK occurs 12s (tEOCTEST = 12s) after the falling edge of CS. If FO is driven by an external oscillator of frequency fEOSC, then tEOCTEST = 3.6/fEOSC. If CS remains LOW longer than tEOCTEST , the first rising edge of SCK will occur and the conversion result is shifted out the SDO pin on the falling edge of SCK. The serial input word (SDI) is shifted into the device on the rising edge of SCK. After the 32nd rising edge of SCK a new conversion automatically begins. SDO goes HIGH (EOC = 1) and SCK 2492fb 23 LTC2492 APPLICATIONS INFORMATION 2.7V TO 5.5V 12 10F REFERENCE VOLTAGE 0.1V TO VCC 13 14 8 9 ANALOG INPUTS 10 11 7 SDI DON'T CARE 1 0 EN SGL ODD A2 A1 A0 EN2 IM FA FB SPD DON'T CARE SDO EOC "0" SIG MSB BIT 20 BIT 19 BIT 18 BIT 17 BIT 0 Hi-Z BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 CONVERSION SLEEP DATA INPUT/OUTPUT CONVERSION 2492 F09 Figure 9. Internal Serial Clock, Single Cycle Operation remains HIGH for the duration of the conversion cycle. Once the conversion is complete, the cycle repeats. Typically, CS remains LOW during the data output state. However, the data output state may be aborted by pulling CS HIGH any time between the 1st rising edge and the 32nd falling edge of SCK (see Figure 10). On the rising edge of CS, the device aborts the data output state and immediately initiates a new conversion. In order to program a new input channel, 8 SCK clock pulses are required. If the data output sequence is aborted prior to the 8th falling edge of SCK, the new input data is ignored and the previously selected input channel remains valid. If the rising edge of CS occurs after the 8th falling edge of SCK, the new input channel is loaded and valid for the next conversion cycle. If CS goes high between the 8th falling edge and the 16th falling edge of SCK, the new channel is still loaded, but the converter configuration remains unchanged. In order to program both the input channel and converter configuration, CS must go high after the 16th falling edge of SCK (at this point all data has been shifted into the device). Internal Serial Clock, 3-Wire I/O, Continuous Conversion. This timing mode uses a 3-wire interface. The conversion result is shifted out of the device by an internally generated serial clock (SCK) signal (see Figure 11). In this case, CS is permanently tied to ground, simplifying the user interface or transmission over an isolation barrier. The internal serial clock mode is selected at the end of the power-on reset (POR) cycle. The POR cycle is concluded approximately 4ms after VCC exceeds 2V. An internal weak pull-up is active during the POR cycle; therefore, the internal serial clock timing mode is automatically selected if SCK is floating or driven HIGH. During the conversion, the SCK and the serial data output pin (SDO) are HIGH (EOC = 1). Once the conversion is complete, SCK and SDO go LOW (EOC = 0) indicating the conversion has finished and the device has entered the sleep state. The device remains in the sleep state a minimum amount of time (1/2 the internal SCK period) then immediately begins outputting and inputting data. 2492fb 24 LTC2492 APPLICATIONS INFORMATION 2.7V TO 5.5V 12 10F REFERENCE VOLTAGE 0.1V TO VCC 13 14 8 9 ANALOG INPUTS 10 11 7 SDI DON'T CARE 1 0 EN SGL ODD A2 A1 A0 EN2 IM FA FB SPD DON'T CARE SDO EOC "0" SIG MSB BIT 20 BIT 19 BIT 18 BIT17 BIT 19 BIT 19 Hi-Z BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 CONVERSION SLEEP DATA INPUT/OUTPUT CONVERSION 2492 F10 Figure 10. Internal Serial Clock, Reduced Data Output Length with Valid Channel and Configuration Selection 2.7V TO 5.5V 12 10F REFERENCE VOLTAGE 0.1V TO VCC 13 14 8 9 ANALOG INPUTS 10 11 7 VCC LTC2492 REF+ REF - CH0 CH1 CH2 CH3 COM GND 6 SDO CS 5 4 SDI SCK 2 3 3-WIRE SPI INTERFACE FO 1 = EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR VCC OPTIONAL 10k 0.1F CS 1 SCK (INTERNAL) 2 3 4 5 6 7 8 9 10 11 12 13 14 32 SDI DON'T CARE 1 0 EN SGL ODD A2 A1 A0 EN2 IM FA FB SPD DON'T CARE SDO EOC "0" SIG MSB BIT 20 BIT 19 BIT 18 BIT 17 BIT 0 CONVERSION 2492 F11 BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 CONVERSION DATA INPUT/OUTPUT Figure 11. Internal Serial Clock, Continuous Operation 2492fb 25 LTC2492 APPLICATIONS INFORMATION The input data is shifted through the SDI pin on the rising edge of SCK (including the first rising edge) and the output data is shifted out the SDO pin on the falling edge of SCK. The data input/output cycle is concluded and a new conversion automatically begins after the 32nd rising edge of SCK. During the next conversion, SCK and SDO remain HIGH until the conversion is complete. The Use of a 10k Pull-Up on SCK for Internal SCK Selection If CS is pulled HIGH while the converter is driving SCK LOW, the internal pull-up is not available to restore SCK to a logic HIGH state if SCK is floating. This will cause the device to exit the internal SCK mode on the next falling edge of CS. This can be avoided by adding an external 10k pull-up resistor to the SCK pin. Whenever SCK is LOW, the LTC2492's internal pull-up at SCK is disabled. Normally, SCK is not externally driven if the device is operating in the internal SCK timing mode. However, certain applications may require an external driver on SCK. If the driver goes Hi-Z after outputting a LOW signal, the internal pull-up is disabled. An external 10k pull-up resistor prevents the device from exiting the internal SCK mode under this condition. A similar situation may occur during the sleep state when CS is pulsed HIGH-LOW-HIGH in order to test the conversion status. If the device is in the sleep state (EOC = 0), SCK will go LOW. If CS goes HIGH before the time tEOCtest , the internal pull-up is activated. If SCK is heavily loaded, the internal pull-up may not restore SCK to a HIGH state before the next falling edge of CS. The external 10k pull-up resistor prevents the device from exiting the internal SCK mode under this condition. PRESERVING THE CONVERTER ACCURACY The LTC2492 is designed to reduce as much as possible sensitivity to device decoupling, PCB layout, anti-aliasing circuits, line frequency perturbations, and temperature sensitivity. In order to achieve maximum performance a few simple precautions should be observed. Digital Signal Levels The LTC2492's digital interface is easy to use. Its digital inputs SDI, FO , CS, and SCK (in external serial clock mode) accept standard CMOS logic levels. Internal hysteresis circuits can tolerate edge transition times as slow as 100s. The digital input signal range is 0.5V to VCC - 0.5V. During transitions, the CMOS input circuits draw dynamic current. For optimal performance, application of signals to the serial data interface should be reserved for the sleep and data output periods. During the conversion period, overshoot and undershoot of fast digital signals applied to both the serial digital interface and the external oscillator pin (FO) may degrade the converter performance. Undershoot and overshoot occur due to impedance mismatch of the circuit board trace at the converter pin when the transition time of an external control signal is less than twice the propagation delay from the driver to the input pin. For reference, on a regular FR-4 board, the propagation delay is approximately 183ps/inch. In order to prevent overshoot, a driver with a 1ns transition time must be connected to the converter through a trace shorter than 2.5 inches. This becomes difficult when shared control lines are used and multiple reflections occur. Parallel termination near the input pin of the LTC2492 will eliminate this problem, but will increase the driver power dissipation. A series resistor from 27 to 54 (depending on the trace impedance and connection) placed near the driver will also eliminate over/under shoot without additional driver power dissipation. For many applications, the serial interface pins (SCK, SDI, CS, FO) remain static during the conversion cycle and no degradation occurs. On the other hand, if an external oscillator is used (FO driven externally) it is active during the conversion cycle. Moreover, the digital filter rejection is minimal at the clock rate applied to FO . Care must be taken to ensure external inputs and reference lines do not cross this signal or run near it. These issues are avoided when using the internal oscillator. 2492fb 26 LTC2492 APPLICATIONS INFORMATION Driving the Input and Reference The input and reference pins of the LTC2492 are connected directly to a switched capacitor network. Depending on the relationship between the differential input voltage and the differential reference voltage, these capacitors are switched between these four pins. Each time a capacitor is switched between two of these pins, a small amount of charge is transferred. A simplified equivalent circuit is shown in Figure 12. When using the LTC2492's internal oscillator, the input capacitor array is switched at 123kHz. The effect of the charge transfer depends on the circuitry driving the input/ reference pins. If the total external RC time constant is less than 580ns the errors introduced by the sampling process are negligible since complete settling occurs. Typically, the reference inputs are driven from a low impedance source. In this case, complete settling occurs even with large external bypass capacitors. The inputs (CH0 to CH3, COM), on the other hand, are typically driven from larger source resistances. Source resistances up to 10k may interface directly to the LTC2492 and settle completely; however, the addition of external capacitors at the input INPUT MULTIPLEXER 100 INTERNAL SWITCH NETWORK 10k terminals in order to filter unwanted noise (anti-aliasing) results in incomplete settling. Automatic Differential Input Current Cancellation In applications where the sensor output impedance is low (up to 10k with no external bypass capacitor or up to 500 with 0.001F bypass), complete settling of the input occurs. In this case, no errors are introduced and direct digitization is possible. For many applications, the sensor output impedance combined with external input bypass capacitors produces RC time constants much greater than the 580ns required for 1ppm accuracy. For example, a 10k bridge driving a 0.1F capacitor has a time constant an order of magnitude greater than the required maximum. The LTC2492 uses a proprietary switching algorithm that forces the average differential input current to zero independent of external settling errors. This allows direct digitization of high impedance sensors without the need of buffers. The switching algorithm forces the average input current on the positive input (IIN+) to be equal to the average input current on the negative input (IIN-). Over the complete IIN+ IN+ I IN+ () ( AVG = I IN- () AVG = VIN(CM) - VREF(CM) 0.5 * REQ I REF + IIN- IN- 100 10k where : ) 1.5VREF + VREF(CM) - VIN(CM) 0.5 * REQ ( )- AVG VIN2 VREF * REQ VREF = REF + - REF - REF + - REF - VREF(CM) = 2 CEQ 12pF IREF+ REF+ 10k VIN = IN+ - IN- , WHERE IN+ AND IN- ARE THE SELECTED INPUT CHANNELS IN+ - IN- VIN(CM) = 2 REQ = 2.71M INTERNAL OSCILLATOR 60Hz MODE REQ = 2.98M INTERNAL OSCILLATOR 50Hz/60Hz MODE REQ = 0.833 * 1012 /fEOSC EXTERNAL OSCILLATOR IREF- REF- 10k 2492 F12 ( ) SWITCHING FREQUENCY fSW = 123kHz INTERNAL OSCILLATOR fSW = 0.4 * fEOSC EXTERNAL OSCILLATOR Figure 12. LTC2492 Equivalent Analog Input Circuit 2492fb 27 LTC2492 APPLICATIONS INFORMATION conversion cycle, the average differential input current (IIN+ - IIN-) is zero. While the differential input current is zero, the common mode input current (IIN+ + IIN-)/2 is proportional to the difference between the common mode input voltage (VIN(CM)) and the common mode reference voltage (VREF(CM)). In applications where the input common mode voltage is equal to the reference common mode voltage, as in the case of a balanced bridge, both the differential and common mode input currents are zero. The accuracy of the converter is not compromised by settling errors. In applications where the input common mode voltage is constant but different from the reference common mode voltage, the differential input current remains zero while the common mode input current is proportional to the difference between VIN(CM) and VREF(CM). For a reference common mode voltage of 2.5V and an input common mode of 1.5V, the common mode input current is approximately 0.74A. This common mode input current does not degrade the accuracy if the source impedances tied to IN + and IN - are matched. Mismatches in source impedance lead to a fixed offset error but do not effect the linearity or full scale reading. A 1% mismatch in a 1k source resistance leads to a 74V shift in offset voltage. In applications where the common mode input voltage varies as a function of the input signal level (single-ended type sensors), the common mode input current varies proportionally with input voltage. For the case of balanced input impedances, the common mode input current effects are rejected by the large CMRR of the LTC2492, leading to little degradation in accuracy. Mismatches in source impedances lead to gain errors proportional to the difference between the common mode input and common mode reference. 1% mismatches in 1k source resistances lead to gain errors on the order of 15ppm. Based on the stability of the internal sampling capacitors and the accuracy of the internal oscillator, a one-time calibration will remove this error. In addition to the input sampling current, the input ESD protection diodes have a temperature dependent leakage current. This current, nominally 1nA (10nA Max), results in a small offset shift. A 1k source resistance will create a 1V typical and a 10V maximum offset voltage. Reference Current Similar to the analog inputs, the LTC2492 samples the differential reference pins (REF+ and REF-) transferring small amounts of charge to and from these pins, thus producing a dynamic reference current. If incomplete settling occurs (as a function the reference source resistance and reference bypass capacitance) linearity and gain errors are introduced. For relatively small values of external reference capacitance (CREF < 1nF), the voltage on the sampling capacitor settles for reference impedances of many k (if CREF = 100pF up to 10k will not degrade the performance) (see Figures 13 and 14). 90 80 70 +FS ERROR (ppm) 60 50 40 30 20 10 0 -10 0 10 1k 100 RSOURCE () 10k 100k 2492 F13 VCC = 5V VREF = 5V VIN+ = 3.75V VIN- = 1.25V FO = GND TA = 25C CREF = 0.01F CREF = 0.001F CREF = 100pF CREF = 0pF Figure 13. +FS Error vs RSOURCE at VREF (Small CREF) 10 0 -10 -FS ERROR (ppm) -20 -30 -40 -50 VCC = 5V -60 VREF = 5V V + = 1.25V -70 VIN- = 3.75V IN -80 FO = GND TA = 25C -90 10 0 CREF = 0.01F CREF = 0.001F CREF = 100pF CREF = 0pF 1k 100 RSOURCE () 10k 100k 2492 F14 Figure 14. -FS Error vs RSOURCE at VREF (Small CREF) 2492fb 28 LTC2492 APPLICATIONS INFORMATION In cases where large bypass capacitors are required on the reference inputs (CREF > 0.01F) full-scale and linearity errors are proportional to the value of the reference resistance. Every ohm of reference resistance produces a full-scale error of approximately 0.5ppm (while operating in simultaneous 50Hz/60Hz mode) (see Figures 15 and 16). If the input common mode voltage is equal to the reference common mode voltage, a linearity error of approximately 0.67ppm per 100 of reference resistance results (see Figure 17). In applications where the input and reference 500 VCC = 5V VREF = 5V VIN+ = 3.75V VIN- = 1.25V FO = GND TA = 25C CREF = 1F, 10F 10 VCC = 5V 8 VREF = 5V VIN(CM) = 2.5V 6 T = 25C A 4 CREF = 10F 2 0 -2 -4 -6 -8 -10 -0.5 -0.3 0.1 -0.1 VIN/VREF 0.3 0.5 2492 F17 R = 1k INL (ppm OF VREF) R = 500 R = 100 400 +FS ERROR (ppm) 300 CREF = 0.1F Figure 17. INL vs Differential Input Voltage and Reference Source Resistance for CREF > 1F 200 CREF = 0.01F 100 common mode voltages are different, the errors increase. A 1V difference in between common mode input and common mode reference results in a 6.7ppm INL error for every 100 of reference resistance. In addition to the reference sampling charge, the reference ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (10nA max) results in a small gain error. A 100 reference resistance will create a 0.5V full scale error. Normal Mode Rejection and Anti-aliasing 0 0 200 600 400 RSOURCE () 800 1000 2492 F15 Figure 15. +FS Error vs RSOURCE at VREF (Large CREF) 0 -100 -FS ERROR (ppm) CREF = 0.01F -200 CREF = 1F, 10F VCC = 5V VREF = 5V VIN+ = 1.25V VIN- = 3.75V FO = GND TA = 25C 0 200 600 400 RSOURCE () CREF = 0.1F -300 -400 One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with a large oversample ratio, the LTC2492 significantly simplifies anti-aliasing filter requirements. Additionally, the input current cancellation feature allows external low pass filtering without degrading the DC performance of the device. -500 800 1000 2492 F16 Figure 16. -FS Error vs RSOURCE at VREF (Large CREF) 2492fb 29 LTC2492 APPLICATIONS INFORMATION The SINC4 digital filter provides excellent normal mode rejection at all frequencies except DC and integer multiples of the modulator sampling frequency (fS) (see Figures 18 and 19). The modulator sampling frequency is fS = 15,360Hz while operating with its internal oscillator and fS = FEOSC/20 when operating with an external oscillator of frequency FEOSC. When using the internal oscillator, the LTC2492 is designed to reject line frequencies. As shown in Figure 20, rejection nulls occur at multiples of frequency fN, where fN is 0 INPUT NORMAL MODE REJECTION (dB) INPUT NORMAL MODE REJECTION (dB) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS11fS12fS DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 2492 F18 determined by the input control bits FA and FB (fN = 50Hz or 60Hz or 55Hz for simultaneous rejection). Multiples of the modulator sampling rate (fS = fN * 256) only reject noise to 15dB (see Figure 21); if noise sources are present at these frequencies anti-aliasing will reduce their effects. The user can expect to achieve this level of performance using the internal oscillator, as shown in Figures 22, 23, and 24. Measured values of normal mode rejection are shown superimposed over the theoretical values in all three rejection modes. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 fN 2fN 3fN 4fN 5fN 6fN 7fN INPUT SIGNAL FREQUENCY (Hz) 8fN fN = fEOSC/5120 2492 F20 Figure 18. Input Normal Mode Rejection, Internal Oscillator and 50Hz Rejection Mode 0 INPUT NORMAL MODE REJECTION (dB) Figure 20. Input Normal Mode Rejection at DC 0 INPUT NORMAL MODE REJECTION (dB) 0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 2492 F19 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 250fN 252fN 254fN 256fN 258fN 260fN 262fN INPUT SIGNAL FREQUENCY (Hz) 2492 F21 Figure 19. Input Normal Mode Rejection, Internal Oscillator and 60Hz Rejection Mode Figure 21. Input Normal Mode Rejection at fS = 256 * fN 2492fb 30 LTC2492 APPLICATIONS INFORMATION 0 NORMAL MODE REJECTION (dB) -20 -40 -60 -80 -100 -120 MEASURED DATA CALCULATED DATA VCC = 5V VREF = 5V VIN(CM) = 2.5V VIN(P-P) = 5V TA = 25C 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 INPUT FREQUENCY (Hz) 2492 F22 Figure 22. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% (60Hz Notch) Traditional high order delta-sigma modulators suffer from potential instabilities at large input signal levels. The proprietary architecture used for the LTC2492 third order modulator resolves this problem and guarantees stability with input signals 150% of full-scale. In many industrial applications, it is not uncommon to have microvolt level signals superimposed over unwanted error sources with several volts of peak-to-peak noise. Figures 25 and 26 show measurement results for the rejection of a 7.5V peak-to-peak noise source (150% of full scale) applied to the LTC2492. From these curves, it is shown that the rejection performance is maintained even in extremely noisy environments. 0 NORMAL MODE REJECTION (dB) -20 -40 -60 -80 -100 -120 VIN(P-P) = 5V VIN(P-P) = 7.5V (150% OF FULL SCALE) 0 NORMAL MODE REJECTION (dB) -20 -40 -60 -80 -100 -120 MEASURED DATA CALCULATED DATA VCC = 5V VREF = 5V VIN(CM) = 2.5V VIN(P-P) = 5V TA = 25C VCC = 5V VREF = 5V VIN(CM) = 2.5V TA = 25C 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 INPUT FREQUENCY (Hz) 2492 F23 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 INPUT FREQUENCY (Hz) 2492 F25 Figure 23. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% (50Hz Notch) Figure 25. Measure Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% (60Hz Notch) 0 NORMAL MODE REJECTION (dB) -20 -40 -60 -80 -100 -120 MEASURED DATA CALCULATED DATA NORMAL MODE REJECTION (dB) VCC = 5V VREF = 5V VIN(CM) = 2.5V VIN(P-P) = 5V TA = 25C 0 -20 -40 -60 -80 -100 -120 VIN(P-P) = 5V VIN(P-P) = 7.5V (150% OF FULL SCALE) VCC = 5V VREF = 5V VIN(CM) = 2.5V TA = 25C 0 20 40 60 80 100 120 140 INPUT FREQUENCY (Hz) 160 180 200 220 2492 F24 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 INPUT FREQUENCY (Hz) 2492 F26 Figure 24. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% (50Hz/60Hz Notch) Figure 26. Measure Input Normal Mode Rejection vs Input Frequency with input Perturbation of 150% (50Hz Notch) 2492fb 31 LTC2492 APPLICATIONS INFORMATION Using the 2x speed mode of the LTC2492 alters the rejection characteristics around DC and multiples of fS . The device bypasses the offset calibration in order to increase the output rate. The resulting rejection plots are shown in Figures 27 and 28. 1x type frequency rejection can be achieved using the 2x mode by performing a running average of the conversion results (see Figure 29). Output Data Rate When using its internal oscillator, the LTC2492 produces up to 7.5 samples per second (sps) with a notch frequency of 60Hz. The actual output data rate depends upon the length of the sleep and data output cycles which are controlled by the user and can be made insignificantly short. When operating with an external conversion clock (FO connected to an external oscillator), the LTC2492 output data rate can be increased. The duration of the conversion cycle is 41036/fEOSC. If fEOSC = 307.2kHz, the converter behaves as if the internal oscillator is used. An increase in fEOSC over the nominal 307.2kHz will translate into a proportional increase in the maximum output data rate (up to a maximum of 100sps). The increase in output 0 INPUT NORMAL REJECTION (dB) INPUT NORMAL REJECTION (dB) 0 fN 2fN 3fN 4fN 5fN 6fN 7fN INPUT SIGNAL FREQUENCY (fN) 8fN -20 -40 -60 -80 rate leads to degradation in offset, full-scale error, and effective resolution as well as a shift in frequency rejection. When using the integrated temperature sensor, the internal oscillator should be used or an external oscillator, fEOSC = 307.2kHz maximum. A change in fEOSC results in a proportional change in the internal notch position. This leads to reduced differential mode rejection of line frequencies. The common mode rejection of line frequencies remains unchanged, thus fully differential input signals with a high degree of symmetry on both the IN+ and IN- pins will continue to reject line frequency noise. An increase in fEOSC also increases the effective dynamic input and reference current. External RC networks will continue to have zero differential input current, but the time required for complete settling (580ns for fEOSC = 307.2kHz) is reduced, proportionally. Once the external oscillator frequency is increased above 1MHz (a more than 3x increase in output rate) the effectiveness of internal auto calibration circuits begins to degrade. This results in larger offset errors, full scale errors, and decreased resolution (see Figures 30 to 37). 0 -20 -40 -60 -80 -100 -120 248 250 252 254 256 258 260 262 264 INPUT SIGNAL FREQUENCY (fN) 2492 F28 -100 -120 2492 F27 Figure 27. Input Normal Mode Rejection 2x Speed Mode Figure 28. Input Normal Mode Rejection 2x Speed Mode 2492fb 32 LTC2492 APPLICATIONS INFORMATION -70 NORMAL MODE REJECTION (dB) -80 NO AVERAGE -90 -100 -110 -120 -130 -140 60 62 54 56 58 48 50 52 DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 2492 F29 50 40 30 OFFSET ERROR (ppm OF VREF) +FS ERROR (ppm OF VREF) VIN(CM) = VREF(CM) VCC = VREF = 5V VIN = 0V FO = EXT CLOCK TA = 85C 3500 3000 2500 VIN(CM) = VREF(CM) VCC = VREF = 5V FO = EXT CLOCK TA = 85C 2000 1500 1000 500 TA = 25C WITH RUNNING AVERAGE 20 10 0 TA = 25C -10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2492 F30 0 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2492 F31 Figure 29. Input Normal Mode Rejection 2x Speed Mode with and Without Running Averaging 0 -500 -FS ERROR (ppm OF VREF) RESOLUTION (BITS) -1000 TA = 25C TA = 85C Figure 30. Offset Error vs Output Data Rate and Temperature 24 TA = 25C 22 TA = 85C RESOLUTION (BITS) 20 18 16 14 12 10 VIN(CM) = VREF(CM) VCC = VREF = 5V VIN = 0V FO = EXT CLOCK RES = LOG 2 (VREF/NOISERMS) 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2492 F33 Figure 31. +FS Error vs Output Data Rate and Temperature 22 20 18 TA = 85C 16 14 VIN(CM) = VREF(CM) 12 VCC = VREF = 5V FO = EXT CLOCK RES = LOG 2 (VREF/INLMAX) 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2492 F34 -1500 -2000 TA = 25C -2500 -3000 VIN(CM) = VREF(CM) VCC = VREF = 5V FO = EXT CLOCK 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2492 F32 -3500 Figure 32.-FS Error vs Output Data Rate and Temperature 20 OFFSET ERROR (ppm OF VREF) VIN(CM) = VREF(CM) VIN = 0V 15 FO = EXT CLOCK TA = 25C RESOLUTION (BITS) 10 VCC = VREF = 5V 5 0 -5 VCC = 5V, VREF = 2.5V -10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2492 F35 Figure 33. Resolution (NoiseRMS 1LSB) vs Output Data Rate and Temperature 24 VCC = VREF = 5V 22 RESOLUTION (BITS) 20 18 16 14 VIN(CM) = VREF(CM) VIN = 0V FO = EXT CLOCK 12 T = 25C A RES = LOG 2 (VREF/NOISERMS) 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2492 F36 Figure 34. Resolution (INLMAX 1LSB) vs Output Data Rate and Temperature 22 20 VCC = 5V, VREF = 2.5V 18 VCC = VREF = 5V 16 VCC = 5V, VREF = 2.5V VIN(CM) = VREF(CM) 14 VIN = 0V REF- = GND 12 FO = EXT CLOCK TA = 25C RES = LOG 2 (VREF/INLMAX) 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2492 F37 Figure 35. Offset Error vs Output Data Rate and Reference Voltage Figure 36. Resolution (NoiseRMS 1LSB) vs Output Data Rate and Reference Voltage Figure 37. Resolution (INLMAX 1LSB) vs Output Data Rate and Reference Voltage 2492fb 33 LTC2492 APPLICATIONS INFORMATION Easy Drive ADCs Simplify Measurement of High Impedance Sensors Delta-Sigma ADCs, with their high accuracy and high noise immunity, are ideal for directly measuring many types of sensors. Nevertheless, input sampling currents can overwhelm high source impedances or low-bandwidth, micropower signal conditioning circuits. The LTC2492 solves this problem by balancing the input currents, thus simplifying or eliminating the need for signal conditioning circuits. A common application for a delta-sigma ADC is thermistor measurement. Figure 38 shows two examples of thermistor digitization benefiting from the Easy Drive technology. The first circuit (applied to input channels CH0 and CH1) uses balanced reference resistors in order to balance the common mode input/reference voltage and balance the differential input source resistance. If reference resistors R1 and R4 are exactly equal, the input current is zero and no errors result. If these resistors have a 1% tolerance, the maximum error in measured resistance is 1.6 due to a shift in common mode voltage; far less than the 1% error of the reference resistors themselves. No amplifier is required, making this an ideal solution in micropower applications. Easy Drive also enables very low power, low bandwidth amplifiers to drive the input to the LTC2492. As shown in Figure 38, CH2 is driven by the LT1494. The LT1494 has excellent DC specs for an amplifier with 1.5A supply current (the maximum offset voltage is 150V and the open loop gain is 100,000). Its 2kHz bandwidth makes it unsuitable for driving conventional delta sigma ADCs. Adding a 1k, 0.1F filter solves this problem by providing a charge reservoir that supplies the LTC2492 instantaneous current, while the 1k resistor isolates the capacitive load from the LT1494. Conventional delta sigma ADCs input sampling current lead to DC errors as a result of incomplete settling in the external RC network. The Easy Drive technology cancels the differential input current. By balancing the negative input (CH3) with a 1k, 0.1F network errors due to the common mode input current are cancelled. 2492fb 34 LTC2492 PACKAGE DESCRIPTION DE Package 14-Lead Plastic DFN (4mm x 3mm) (Reference LTC DWG # 05-08-1708 Rev A) 0.70 0.05 3.30 0.05 1.70 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC 3.00 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 3.60 0.05 2.20 0.05 4.00 0.10 (2 SIDES) R = 0.05 TYP R = 0.115 TYP 8 14 0.40 0.10 3.00 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) 3.30 0.10 1.70 0.10 PIN 1 NOTCH R = 0.20 OR 0.35 45 CHAMFER (DE14) DFN 0806 REV B 7 0.200 REF 0.75 0.05 3.00 REF 0.00 - 0.05 1 0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 2492fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 35 LTC2492 TYPICAL APPLICATION 5V R1 51.1k C4 0.1F IIN+ = 0 R3 10k TO 100k 10F 13 0.1F C3 0.1F 5V 102k 5V R4 51.1k IIN- = 0 14 8 9 10 11 1k LT1494 0.1F 1k 0.1F 7 5V 12 VCC LTC2492 REF + REF - CH0 CH1 CH2 CH3 COM GND 2492 F38 FO 1 = EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR SDI SCK 5 2 3 3-WIRE SPI INTERFACE SDO CS 4 + 0.1F 10k TO 100k 6 - Figure 38. Easy Drive ADCs Simplify Measurement of High Impedance Sensors RELATED PARTS PART NUMBER LT1236A-5 LT1460 LT1790 LTC2400 LTC2410 LTC2411/ LTC2411-1 LTC2413 LTC2440 LTC2442 LTC2449 LTC2480 LTC2481 LTC2482 LTC2483 LTC2484 LTC2485 LTC2488 LTC2496/ LTC2498 DESCRIPTION Precision Bandgap Reference, 5V Micropower Series Reference Micropower SOT-23 Low Dropout Reference Family 24-Bit, No Latency ADC in SO-8 24-Bit, No Latency ADC with Differential Inputs 24-Bit, No Latency ADCs with Differential Inputs in MSOP 24-Bit, No Latency ADC with Differential Inputs High Speed, Low Noise 24-Bit ADC 24-Bit, High Speed 2-Channel and 4-Channel ADC with Integrated Amplifier 24-Bit, High Speed 8-Channel and 16-Channel ADC 16-Bit ADC with Easy Drive Inputs, 600nV Noise, Programmable Gain, and Temperature Sensor 16-Bit ADC with Easy Drive Inputs, 600nV Noise, I2C Interface, Programmable Gain, and Temperature Sensor 16-Bit ADC with Easy Drive Inputs 16-Bit ADC with Easy Drive Inputs, and I2C Interface 24-Bit ADC with Easy Drive Inputs 24-Bit ADC with Easy Drive Inputs, I2C Interface, and Temperature Sensor 16-Channel/8-Channel 16-Bit/24-Bit ADC with Easy Drive Inputs, and SPI Interface COMMENTS 0.05% Max Initial Accuracy, 5ppm/C Drift 0.075% Max Initial Accuracy, 10ppm/C Max Drift 0.05% Max Initial Accuracy, 10ppm/C Max Drift 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200A 0.8VRMS Noise, 2ppm INL 1.45VRMS Noise, 4ppm INL, Simultaneous 50Hz/60Hz Rejection (LTC2411-1) Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise 3.5kHz Output Rate, 200nV Noise, 24.6 ENOBs 8kHz Output Rate, 220nV Noise, Simultaneous 50Hz/60Hz Rejection 8kHz Output Rate, 200nV Noise, Simultaneous 50Hz/60Hz Rejection Pin Compatible with LTC2482/LTC2484 Pin Compatible with LTC2483/LTC2485 Pin Compatible with LTC2480/LTC2484 Pin Compatible with LTC2481/LTC2485 Pin Compatible with LTC2480/LTC2482 Pin Compatible with LTC2481/LTC2483 2-Channel and 4-Channel 16-Bit ADC with Easy Drive Inputs Pin Compatible with LTC2492 Timing Compatible with LTC2492 2492fb 36 Linear Technology Corporation (408) 432-1900 FAX: (408) 434-0507 LT 1008 REV B* PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com (c) LINEAR TECHNOLOGY CORPORATION 2006 |
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